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74ABT16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
April 1992 Revised November 1999
74ABT16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT16244 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Individual 3STATE control inputs can be shorted together for 8-bit or 16-bit operation.
Features
s Separate control logic for each nibble s 16-bit version of the ABT244 s Outputs sink capability of 64 mA, source capability of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability
Ordering Code:
Order Number 74ABT16244CSSC 74ABT16244CMTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices are also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names OEn I0-I15 O0-O15 Description Output Enable Inputs (Active LOW) Inputs Outputs
(c) 1999 Fairchild Semiconductor Corporation
DS010985
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74ABT16244
Truth Tables
Inputs OE1 L L H Inputs OE2 L L H Inputs OE3 L L H Inputs OE4 L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Functional Description
Outputs I0-I3 L H X O0-O3 L H Z Outputs I4-I7 L H X O4-O7 L H Z Outputs I8-I11 L H X O8-O11 L H Z Outputs I12-I15 L H X O12-O15 L H Z The ABT16244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.
Logic Diagram
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74ABT16244
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) twice the rated IOL (mA) -500 mA 10V -0.5V to 5.5V -0.5V to VCC -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (V/t) Data Input Enable Input 50 mV/ns 20 mV/ns -40C to +85C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test 4.75 2.5 2.0 0.55 1 1 7 -1 -1 Min 2.0 0.8 -1.2 Typ Max Units V V V V V V A A A V A A mA A A mA mA mA mA mA A Max Min Min Min Min Max Max Max 0.0 VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -3 mA IOH = -32 mA IOL = 64 mA VIN = 2.7V (Note 3) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 3) VIN = 0.0V IID = 1.9 A All Other Pins Grounded Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current -100 10 -10 -275 50 100 2.0 60 2.0 Outputs Enabled Outputs 3-STATE Outputs 3-STATE 2.5 2.5 50 0 - 5.5V VOUT = 2.7V; OEn = 2.0V 0 - 5.5V VOUT = 0.5V; OEn = 2.0V Max Max 0.0 Max Max Max VOUT = 0.0V VOUT = VCC VOUT = 5.5V All Other Pins GND All Outputs HIGH All Outputs LOW OEn = VCC All Others at VCC or GND Additional ICC/Input VI = VCC - 2.1V Enable Input VI = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCC or GND ICCD Dynamic ICC (Note 3)
Note 3: Guaranteed but not tested.
No Load 0.1
mA/ MHz
Max
Outputs Open, OEn = GND One Bit Toggling, 50% Duty Cycle
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74ABT16244
DC Electrical Characteristics
Symbol VOLP VOLV VOHV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage -1.3 2.7 2.0 Min Typ 0.4 -1.0 3.0 1.4 1.2 0.8 Max 0.7 Units V V V V V VCC 5.0 5.0 5.0 5.0 5.0 Conditions CL = 50 pF, RL = 500 TA = 25C (Note 4) TA = 25C (Note 4) TA = 25C (Note 5) TA = 25C (Note 6) TA = 25C (Note 6)
Note 4: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 5: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 6: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V ILD), 0V to threshold (VIHD ). Guaranteed, but not tested.
AC Electrical Characteristics
TA=+25C Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Data to Outputs Output Enable Time Output Disable Time 1.0 1.0 1.5 1.5 1.0 1.0 VCC=+5V CL = 50 pF Typ 2.3 2.7 3.5 3.5 4.2 3.2 Max 3.9 3.9 6.3 6.3 6.7 6.7 Min 1.0 1.0 1.5 1.5 1.0 1.0 TA = -40C to +85C VCC = 4.5V-5.5V CL = 50 pF Max 3.9 3.9 6.3 6.3 6.7 6.7 ns ns ns Units
Extended AC Electrical Characteristics
-40C to +85C VCC = 4.5V-5.5V Symbol Parameter CL = 50 pF 16 Outputs Switching (Note 7) Min fTOGGLE tPLH tPHL tPZH tPZL tPHZ tPLZ Output Disable Time Max Toggle Frequency Propagation Delay Data to Outputs Output Enable Time 1.5 1.5 1.5 1.5 1.0 1.0 Typ 100 5.0 5.3 6.5 6.5 6.7 6.7 1.5 1.5 2.5 2.5 (Note 10) 6.0 6.0 7.8 7.8 2.5 2.5 2.5 2.5 (Note 10) 8.0 8.0 9.5 8.5 Max Min TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 1 Output Switching (Note 8) Max Min TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 16 Outputs Switching (Note 9) Max MHz ns ns ns Units
Note 7: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 8: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 9: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 10: The 3-STATE delay times are dominated by the RC network (500, 250 pF) on the output and have been excluded from the datasheet.
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74ABT16244
Skew
TA = -40C to +85C VCC = 4.5V-5.5V Symbol Parameter CL = 50 pF 16 Outputs Switching (Note 11) Max tOSHL (Note 13) tOSLH (Note 13) tPS (Note 14) tOST (Note 13) tPV (Note 15) Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LH-HL Skew Pin to Pin Skew LH/HL Transitions Device to Device Skew LH/HL Transitions 1.0 1.0 1.5 1.7 2.0 TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 16 Outputs Switching (Note 12) Max 1.5 1.5 1.5 2.0 2.5 ns ns ns ns ns Units
Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) Note 12: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). The specification is guaranteed but not tested. Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested.
Capacitance
Symbol CIN COUT (Note 16) Parameter Input Capacitance Output Capacitance Typ 5.0 9.0 Units pF pF V CC = 5.0V V CC = 5.0V Conditions TA = 25C
Note 16: COUT is measured at frequency f = 1 MHz; per MIL STD-883, Method 3012.
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74ABT16244
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load Amplitude 3.0V Rep Rate 1 MHz tW 500 ns
FIGURE 2. Test Input Pulse Requirements tr 2.5 ns tf 2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms
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74ABT16244
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74ABT16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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